Effect of static power dissipation in burn-in environment on yield of VLSI

The leakage power is expected to increase with scaling of CMOS technology. The increased leakage is a strong function of the elevated temperature and voltage stress. As a consequence; under the burn-in (BI) conditions the elevated leakage power may cause increased post burn-in fallout. In this paper the impact of elevated leakage and technology scaling in burn-in environment on post BI yield is analyzed. We have also shown that to maintain a constant post-BI yield loss, the burn-in temperature should go down by 10/spl deg/C for each technology generation. We also show that at static burn-in conditions, the die temperature is increased exponentially and range of optimal stressed voltage and temperature for fixed post burn-in yield loss is reduced significantly, when CMOS technology is aggressively scaled down.